| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0413
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0291
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0278
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2230-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3677
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3648
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G5-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 |
| filingDate |
2021-04-22^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d4d9be286624dc55ccecf0a4f6e26e04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7fa2f1cf002f782d6fbf62e9b457795a |
| publicationDate |
2021-05-04^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20210049054-A |
| titleOfInvention |
Pulse generation circuit and semiconductor device |
| abstract |
An object of the present invention is to narrow the bezel width of a display device by designing the layout of the gate driver. Two gate drivers are installed on the left and right of the pixel portion. The gate lines are alternately connected to the left and right gate drivers for every M rows. The two gate drivers have a shift register and a demultiplexer composed of a transistor of a single conductivity type. The shift register has k first unit circuits cascaded. The demultiplexer has k second unit circuits to which signals are input from the first unit circuit and M gate lines are connected. The second unit circuit selects one or a plurality of wirings that output an input signal from the first unit circuit from the M gate lines, and outputs a signal from the first unit circuit to the selected wirings. Since the gate signal can be output to the M gate lines from the output of the shift register in one stage, the width of the shift register can be narrowed. |
| priorityDate |
2013-04-04^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |