| abstract |
1,098,468. Integrated circuits. SOCIETE SUISSE POUR L'INDUSTRIE HORLOGERE S.A. March 24, 1965 [March 26, 1964], No. 12579/65. Heading H1K. [Also in Division H3] An integrated circuit (Fig. 1) comprising only insulated gate field effect transistors and capacitors is formed at one surface of a P-type silicon wafer by first diffusing donor material through oxide masking formed using photolithographic techniques to form N zones 2, 3, 4 constituting the source and drain regions of transistors T 1 , T 2 T 3 . Aluminium is then deposited over further oxide masking to ohmically contact the zones at 11 and 12 and is selectively removed by photolithographic techniques to leave only areas 5, 6, 7, 9, and 10. These constitute the gate electrodes of the three transistors and electrodes of capacitors C 1 , C 2 , the other electrodes of which are constituted by portions of the N zones 3 and 4. The disposition of the source regions between pairs of drain regions reduces undesired coupling between adjacent transistors. Formation of inversion layers beneath the connections to the gate electrodes may be avoided by providing P + inserts in the silicon at these points. |