http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201940952-A

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filingDate 2019-02-14^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2019-10-16^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-201940952-A
titleOfInvention Interlayer configuration for narrow-frame electro-optic display backplane with reduced capacitive coupling between T-line and pixel electrode
abstract An electro-optical display includes a pixel electrode array, wherein each column of pixel electrodes is associated with a source line, and the source line is connected to a driving chip by a T line, and the T line is connected to the substrate from a back surface of the substrate through a via. Positive. The interlayers are separated by, for example, a zigzag pattern or a pseudo-random pattern, to reduce the capacitive coupling between the T lines when driving adjacent pixels, for example, when presenting a local character.
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