| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01J2001-4466
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01J2001-444 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0995
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01S17-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01S7-4865
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01J1-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0812
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01S7-4863
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01B11-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G04F10-005 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08 |
| filingDate |
2019-07-10^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_78b379dd47a219c7d38089f7f89beb86
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d79b6969f1cf1fbcf5270da43e9007a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c807517b8ccfb3549c07d67a6258ef3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_60e359f4131910a6ea73af8ea863eefd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_12aec2bc02e14939445c9f2202015065 |
| publicationDate |
2020-02-01^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-202007090-A |
| titleOfInvention |
Self-calibration time-to-digital converter integrated circuit |
| abstract |
A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing. |
| priorityDate |
2018-07-11^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |