http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-202116061-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_eae3034a505868e4f55845e3e3667646 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-124 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-462 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-709 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-124 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-616 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-462 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-75 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-466 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-70 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04N5-378 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-12 |
| filingDate | 2020-09-15^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2f3cabe11c2e86200480d00736e73c20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a156ab6fdb9869194f71b56f4b740cc |
| publicationDate | 2021-04-16^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-202116061-A |
| titleOfInvention | Subrange adc and subrange adc image sensing system |
| abstract | A subrange analog-to-digital converter (ADC) and subrange analog-to-digital converter image sensing system, which converts analog image signal received from a bitline to a digital signal through an ADC comparator. The comparator is shared by a successive approximation register (SAR) ADC coupled to provide M upper output bits (UOB) of the subrange ADC and a ramp ADC coupled to provide N lower output bits (LOB). The digital-to-analog converter (DAC) of the SAR ADC comprises M buffered bit capacitors connected to the comparator. Each buffered bit capacitor comprises a bit capacitor, a bit buffer, and a bit switch controlled by one of the UOB of the SAR ADC. A ramp buffer is coupled between a ramp generator and a ramp capacitor. The ramp capacitor is further coupled to the same comparator. The implementation of ramp buffer and the bit buffers as well as their sharing of the same kind of buffer reduces differential nonlinear (DNL) error of the subrange ADC. |
| priorityDate | 2019-10-02^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID516892 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID453034310 |
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