| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7682
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53252
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-535
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53257
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-4855
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7685
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32133
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53209
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5329 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-535
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 |
| filingDate |
2021-05-04^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c420038f8817048dd97bae7a03df5ecb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0513b516ff01ca59b3f94991705f08d0 |
| publicationDate |
2022-04-01^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-202213688-A |
| titleOfInvention |
Integrated circuit device and method of fabrication thereof |
| abstract |
Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer. |
| priorityDate |
2020-09-29^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |