http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-409258-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_44f82521bd7b49adba4be2e3e4f3b66a |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-08 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4087 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4085 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-10 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 |
| filingDate | 1996-07-23^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-10-21^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d636e0ec68ceb09312f14b84a1a4402b |
| publicationDate | 2000-10-21^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-409258-B |
| titleOfInvention | Semiconductor memory device including divisional decoder circuit composed of NMOS transistors |
| abstract | A semiconductor memory device includes a series circuit (2, 3) composed of a drive MOS transistor (2) as a first MOS transistor and a reset MOS transistor (3) as a second MOS transistor connected in series via a common connection node, a source of the reset MOS transistor being connected to a lower potential power supply, a main word line (MW), and a sub-word line (SW) connected to the common connection node. An address signal includes a first part (21) and a second part (22) and a row address signal section (12) decodes the first part (22) of the address signal to generate a first row address signal (RA) and a second row address signal (inverted RA) having a phase inverse to that of the first row address signal in accordance with the decoding result, and supplies the first row address signal to a drain of the drive MOS transistor (2) and the second row address signal to a gate of a reset MOS transistor (3). A main decoder circuit (11) decodes the second part of the address signal to output a main word line signal to the main word line (MW) in accordance with the decoding result before the row address signal section (12) supplies the first and second row address signals. A third MOS transistor (1) as a transfer section transfers the main word line signal to a gate of the drive MOS transistor (2). A fourth MOS transistor (4) as a preventing section is provided to prevent the sub-word line from floating when there is no main word line signal and the force MOS transistor includes a gate connected to the first row address signal, a drain connected to the main word line, and a source connected to the common connection node. |
| priorityDate | 1995-08-17^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID452858641 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID165166 |
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