| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-16 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08 |
| filingDate |
1998-11-06^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2001-01-01^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ea5eb377b8c2d8ab4f29dc76b2a9e0b6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c01d3ca0645843158607bd4430342141
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ebe39d18013a626c0d106f2a56a93d1d |
| publicationDate |
2001-01-01^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-417304-B |
| titleOfInvention |
Nonvolatile semiconductor memory device whose addresses are selected in a multiple manner |
| abstract |
A block size buffer and block address pre-decoder are provided for a flash memory. At the time of data erase, the size of a block to be erased is input to the block size buffer and a set of block addresses is input to the block address pre-decoder. An output signal of the block size buffer is supplied to and decoded by the block address pre-decoder, a row decoder is controlled based on the result of pre-decoding, and a plurality of addressing including the above block address as a top address are selected in a multiple manner. Then, a plurality of successive blocks are simultaneously selected to simultaneously erase data in the memory cells in the plurality of blocks. |
| priorityDate |
1997-11-06^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |