http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-502396-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6623826fb005ec2357960fdc6dcc8490 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-55 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28568 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-75 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| filingDate | 2001-04-18^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2002-09-11^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_82e4d800a8cc748288537684eb0c753a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_857a6b879a3390d2a8513897e5500a86 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93e77bd6d4624190b21f554dcc031e53 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fcd9d6d9c6295b4d91c26e7d68734f0d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5bea5df345ea7510394ac76dee8ede81 |
| publicationDate | 2002-09-11^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-502396-B |
| titleOfInvention | Method for forming an integrated barrier/plug for a stacked capacitor |
| abstract | A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices. A process for forming an integrated barrier/plug memory cell structure comprising: etching a area in a semiconductor substrate; depositing a conductive barrier/plug material within said etched area, said conductive plug material being selected from the group consisting of titanium nitride, tungsten nitride, titanium aluminum nitride, tantalum silicon nitride, or a combination thereof; planarizing said deposited conductive plug material; depositing a first conductor selected from the group consisting of platinum, the noble metals, alloys of noble metals, alloys of noble metals with noble or non-noble metals, metals whose oxides are conducting, electrically conducting oxides, electrically conductive-oxidation-resistant nitrides and electrically conductive materials whose oxides are insulating; patterning and etching said deposited first conductor; depositing a high dielectric constant material over said patterned and etched first conductor; and depositing a second conductor on said deposited high dielectric constant material. |
| priorityDate | 2000-04-18^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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