http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-535281-B

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filingDate 2001-11-08^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2003-06-01^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_04e2c7b75136759ede047d793683dc30
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publicationDate 2003-06-01^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-535281-B
titleOfInvention Semiconductor integrated circuit device and method of manufacturing the same
abstract The purpose of the present invention is to provide a technology to raise a threshold electric potential of a parasitic MOS of a semiconductor integrated circuit device comprising a high breakdown-strength MISFET. A silicon oxide film 5c is formed on a field oxide film 4 of high breakdown-strength MISFET formation regions HN and HP. As a result, the threshold electric potential of the parasitic MOS formed on the field oxide film 4 is raised. An impurity is implanted for adjusting the threshold value of a low breakdown-strength MISFET with a polycrystal silicon film 111 which is to be a gate electrode of the low breakdown-strength MIFET formed on a gate electrode FG of the high breakdown strength MISFET. As a result, the impurity remains in the gate electrode FG of the high breakdown-strength MISFET, suppressing occurrence of NBT phenomenon.
priorityDate 2000-11-30^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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