http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I291180-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1051 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1057 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4093 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0175 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-13 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0948 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 |
| filingDate | 2005-12-30^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-12-11^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4498272b55949b464040b2178f54fb0c |
| publicationDate | 2007-12-11^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I291180-B |
| titleOfInvention | Semiconductor memory device |
| abstract | A semiconductor memory device according to the present invention can change adjusting timing of ODT operation in convenience and have an optimized ODT timing whether the semiconductor memory device is putted on ether rank of a module. The present invention includes an impedance adjusting unit for adjusting an impedance value of an input pad in response to an impedance selecting signal; an ODT operating control unit for controlling the impedance adjusting unit as generating the impedance selection signal using a decoding signal and an ODT timing signal; a delay adjusting unit for delaying an internal control clock for a predetermined timing to thereby generate the ODT timing signal; and an ODT timing control unit for controlling the delay adjusting unit to decide the value of the predetermined timing according to whether or not the semiconductor memory device is arranged to a first rank or a second rank in a module. |
| priorityDate | 2005-06-30^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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