Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_cbacc56d3364ec74a8622d697ea298f9 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-267 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2013-005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-8615 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-73 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-54 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-33 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-002 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2013-009 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-0012 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-15 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0069 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-8605 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-417 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0097 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-861 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8239 |
filingDate |
2017-06-26^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2018-08-11^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_278a5eabb56fb8fd161e2de6063ee812 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_43f8f1e833ad3365bf43680586e7af80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ae39b6e0cb80f816f6a225aa93d2dcff |
publicationDate |
2018-08-11^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
TW-I632646-B |
titleOfInvention |
Resistive memory element |
abstract |
A resistive memory element comprising: a p-type layer; a tunneling structure formed on the p-type layer; and an N-type layer formed on the tunneling structure; wherein the p-type layer and the N are applied When a bias voltage between the layers is greater than a reset voltage, the resistive memory element is in a reset state, and the bias voltage applied between the P-type layer and the N-type layer is less than a set voltage The resistive memory element is in a set state. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10586831-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I720351-B |
priorityDate |
2017-06-26^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |