| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6a162b65402a9a79580e3ae31dcbf3fa |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K10-88
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K10-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136209
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K71-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K71-611 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K71-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78633
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-122
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K10-468
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-1213
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1248 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| filingDate |
2015-02-16^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-01-01^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d3cc4ba79b3de399e3176e95daee66ac |
| publicationDate |
2019-01-01^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I646669-B |
| titleOfInvention |
Thin film transistor array and manufacturing method thereof |
| abstract |
Provided is a thin film transistor array having good transistor characteristics even when irradiated with light, and a manufacturing method thereof. A thin film transistor array includes: a substrate; a plurality of thin film transistors having at least a gate electrode, a gate insulating film, a source and a drain electrode, a semiconductor layer formed between the source and the drain electrode, and an interlayer on the substrate. An insulating film and an upper pixel electrode; a gate wiring connected to the gate electrode; and a source wiring connected to the source electrode, and a light-shielding insulating layer is formed between adjacent upper pixel electrodes. . |
| priorityDate |
2014-02-21^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |