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filingDate 2017-10-18^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2019-03-11^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_00700442f90f89c722a0a405c1b6f841
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publicationDate 2019-03-11^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-I653710-B
titleOfInvention Method for forming semiconductor structure capable of reducing leakage current
abstract The present disclosure provides a method for mitigating a leakage current of a device including a continuous active region. In some embodiments, the threshold logic type at the cell boundary is inverted by changing the mask logic operation to increase the threshold voltage at the cell boundary. Alternatively, in some examples, a threshold voltage implantation (for example, ion implantation) is performed in a cell boundary and a dummy fin provided at the cell boundary to increase the threshold voltage at the cell boundary. Furthermore, in some embodiments, a SiGe channel is used at the cell boundary to increase the threshold voltage at the cell boundary. In some examples, silicon germanium may be disposed in a substrate at a cell boundary, and / or silicon germanium may be part of a dummy fin disposed at a cell boundary.
priorityDate 2017-08-31^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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