http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I692950-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_399a62424437cdee73e74a007502ec94 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D30-50 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L49-25 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L12-4633 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L45-74 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L49-351 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L12-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L49-3009 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L49-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L45-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L69-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L45-245 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04B3-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L12-741 |
| filingDate | 2018-05-11^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-05-01^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b7611ceb9aa2b4482c30ad8ac73ccf0f |
| publicationDate | 2020-05-01^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I692950-B |
| titleOfInvention | Function-extended wired network device |
| abstract | The present invention discloses a function-expandable wired network device using an external circuit to execute an operation that an Ethernet device can’t execute. An embodiment of the network device includes an Ethernet switch and a Field-Programmable Gate Array (FPGA). The switch includes Ethernet ports including a designated port and a first port and receives a first packet from the first port; and if the first packet carries information that meets prestored information of the switch, the switch amends the first packet to output a second packet to the designated port. The FPGA receives the second packet from the designated port and processes the second packet according to the switch’s amendment to the second packet to output a third packet to the designated port. The switch then processes the third packet according to the FPGA’s amendment to the third packet to output a fourth packet to one of the Ethernet ports. |
| priorityDate | 2018-05-11^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Showing number of triples: 1 to 26 of 26.