| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fa907cbef2178b7f30a042518be6b17b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42344
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3086
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76229
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11524
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11551 |
| filingDate |
2018-08-09^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-05-11^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1fcf986dda982bc8146170e7e14e182e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ef0f51be5c4509bb9b064d23c917c4d0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b8d98e9a04cd9aa8ba6cde1d3f8117b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8ad2ef5ec326a0196b69a99e0683b544
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a0cea35af3ce9d27d06225754c86fbd5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_19877c31a742b1161419d75af48377ad
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_838847d631046f4d82a79dc213b07bf9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_456c3e9d5c6d527889bf2207d18640b3 |
| publicationDate |
2020-05-11^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I693701-B |
| titleOfInvention |
Method to improve channel hole uniformity of a three-dimensional memory device |
| abstract |
Methods and structures of a three-dimensional memory device are disclosed. In an example, a method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes. |
| priorityDate |
2017-08-31^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |