http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I700832-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_623cbbe94020c9a40e63d81ee58993ad |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0882 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0878 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7825 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-43 |
| filingDate | 2018-12-03^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-08-01^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_af9b298a4543599ef074600bcd7c645c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_77fcd5b075b632e7e566fd9034d6cae5 |
| publicationDate | 2020-08-01^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I700832-B |
| titleOfInvention | Multiple gated power mosfet device |
| abstract | The present disclosure provides a power MOSFET device including a multiple gated transistor disposed over a substrate. The multiple gated transistor includes a first transistor cell having a first drain pillar, a first source pillar, and a first gate conductor disposed between the first drain pillar and the first source pillar. The multiple gated transistor further includes a second transistor cell having a second drain pillar, a second source pillar, and a second gate conductor disposed between the second drain pillar and the second source pillar. The multiple gated transistor further includes a first insulator disposed over the substrate and between the first gate conductor and the second gate conductor. The first insulator electrically insulates the second gate conductor from the first gate conductor. During operation, the first transistor cell and the second transistor cell share a common source and a common drain, and conductive states of the first gate conductor and the second gate conductor are controlled separately. |
| priorityDate | 2018-09-13^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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