http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I713202-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_57341227c065dbddd1d3cf801bbaa86a |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11517 |
| filingDate | 2019-01-22^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-12-11^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fb77e607d364bef224c24f50f9813b4a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e8b448143ad2c185a4c30109e2860c5 |
| publicationDate | 2020-12-11^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-I713202-B |
| titleOfInvention | Flash memories and methods for forming the same |
| abstract | A flash memory is provided. The flash memory includes a semiconductor substrate, a floating gate structure on the semiconductor substrate, an inter-gate dielectric layer covering sidewalls and a top surface of the floating gate structure, and a control gate on the inter-gate dielectric layer. The floating gate structure includes a floating gate dielectric layer on the semiconductor substrate, a pair of dielectric spacers on the floating gate dielectric layer, wherein the pair of dielectric spacers have sloped sidewalls that face each other, and a floating gate on the floating gate dielectric layer and between the pair of dielectric spacers. The floating gate has a pair of tips over the respective sloped sidewalls of the pair of dielectric spacers. |
| priorityDate | 2019-01-22^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Showing number of triples: 1 to 36 of 36.