| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_53f347c8f604f15767e8e73fec62095a |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L9-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23P19-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L25-028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L49-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L25-03885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L25-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L9-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L49-111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B23P19-04 |
| filingDate |
2017-10-02^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-04-09^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_80107af2c55c900a439d34c913f17014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_94f53ccac5c267221d9be594ecf740d8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c3c3fcc2740b3c3b07aa15dd5c9c4994
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_edefaa6deb2f23f0710fe492efe63337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2b2b5e1a6af829713edbf8bff5719654
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_288d6d89ff8f7e332deeae69200ccc22 |
| publicationDate |
2019-04-09^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10257121-B1 |
| titleOfInvention |
Full-rate transmitter |
| abstract |
Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11153129-B1 |
| priorityDate |
2017-10-02^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |