| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3086
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0617
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5256
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5258
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5252
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-62
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-22 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-62
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-525
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-308
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 |
| filingDate |
2017-12-08^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-02-25^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eb9e5f1701e0d8f030fc230042b203df
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa57155a94ec485068066724e7721ca7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_20cb38d9cb42b4a5b0c5a6558bd770e5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9077b08a8cf1e345b39793ea956a0c26 |
| publicationDate |
2020-02-25^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10573596-B2 |
| titleOfInvention |
FinFET fuses formed at tight pitch dimensions |
| abstract |
A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10892222-B1 |
| priorityDate |
2017-12-08^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |