http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10657302-B1

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filingDate 2018-04-23^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2020-05-19^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_708b897005f1653334bec0b57598bd0c
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publicationDate 2020-05-19^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-10657302-B1
titleOfInvention Route generation and buffer placement for disjointed power domains in an integrated circuit
abstract The present embodiments relate to buffering signals between disjointed power domains with similar power profiles in an integrated circuit. According to some aspects, embodiments relate to a method in which an electronic design automation (EDA) tool displays a schematic including a plurality of first power domains having a first power profile and a plurality of second power domains having a second power profile. The EDA tool generates graph including a plurality of points and a plurality of edges connecting the points, where the points are located on the plurality of second power domains. The EDA tool selects one route from a plurality of routes from a start node on the graph to an end node on the graph and determines a number of buffers located on the route based on associated distance values and a design violation values.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11449660-B1
priorityDate 2018-04-06^^<http://www.w3.org/2001/XMLSchema#date>
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