| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_70ca3ea7752cc2ae9b2687d93d702a99 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31705
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-2733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-3656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-267
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-2236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-3648
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318533
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-3636 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F30-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-273
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-267
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-317
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-00 |
| filingDate |
2018-04-03^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-09-29^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8d2fb64cac10733ae25ae1bddb385774
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c0d9fa017292bb7c673a2c3b83e0858
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9166d483b06192cbc6f8b75a71b2656a |
| publicationDate |
2020-09-29^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10789153-B2 |
| titleOfInvention |
Debug controller circuit |
| abstract |
A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers. |
| priorityDate |
2018-04-03^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |