| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6032caf960c1a133ff417ef8283115d9 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-097
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-135 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L5-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-135
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10 |
| filingDate |
2017-05-31^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-01-26^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_858060c3c9e4ed6b797a6a127044971d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_abf9470053a557b8681cd51a61273b39
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d324cead89a33248c98555596989655e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_61ce964944eec34a45b72ff47b4d99f8 |
| publicationDate |
2021-01-26^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10901455-B2 |
| titleOfInvention |
Time arbitration circuit |
| abstract |
A time arbitration circuit includes: a comparator including at least first and second inputs and configured to provide at least a first data item relative to the synchronization status of the signals present on the first and second inputs; a clock signal generator connected to an output terminal of the time arbitration circuit and delivering an output clock signal; a control circuit configured to enable or disable delivery of the output clock signal on the output terminal according to the first data item from the comparator and to possibly deliver data relative to the synchronization status according to the first data item; the first and second inputs of the comparator are connected to first and second input terminals of the time arbitration circuit designed to be connected to first and second sources delivering first and second clock signals. |
| priorityDate |
2016-05-31^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |