| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-098 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0605
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8252
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-567
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0727
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-6871 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K17-567
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778 |
| filingDate |
2019-09-19^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-04-06^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_53a1c4fcf706dda08d7bb5e55a845065 |
| publicationDate |
2021-04-06^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10971616-B2 |
| titleOfInvention |
Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same |
| abstract |
Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness. |
| priorityDate |
2018-10-31^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |