http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11004530-B2

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filingDate 2019-04-08^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2021-05-11^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2021-05-11^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-11004530-B2
titleOfInvention Testing through-silicon-vias
abstract Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
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