| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d70433f8686c548ecc973cde0a2673fb |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0069
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-79
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-71 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0023
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-2436
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-003 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-24 |
| filingDate |
2020-02-26^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-08-31^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b5e259008873324bc63f6ac6e3783fa4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dae46b5e7e5aa34f66a513a3621e491b |
| publicationDate |
2021-08-31^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11107527-B1 |
| titleOfInvention |
Reducing sneak current path in crossbar array circuits |
| abstract |
Technologies relating to crossbar array circuits with nTnR design to reduce sneak current path and minimize area size are disclosed. An example crossbar array circuit includes: a first transistor comprising a first source terminal, a first drain terminal and a first gate terminal; a first RRAM device connected to the first source terminal of the first transistor; a second transistor comprising a second source terminal, a second drain terminal and a second gate terminal; a second RRAM device connected to the second source terminal of the second transistor; a word line connected to the first drain terminal of the first transistor and the second drain terminal of the second transistor; a first bit line connected to the first RRAM device; and a second bit line connected to the second RRAM device, wherein the first gate terminal of the first transistor is configured to be connected to a first selective voltage source, and the second gate terminal is configured to be connected to a second selective voltage source. |
| priorityDate |
2020-02-26^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |