| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11575
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11575
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate |
2019-11-26^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-03-01^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f0a9f051847e029ab42e7c3f5cd80109
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a996c99b315d2e2aefdea6e8935b76e |
| publicationDate |
2022-03-01^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11264402-B2 |
| titleOfInvention |
Boundary design to reduce memory array edge CMP dishing effect |
| abstract |
In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of memory devices within an embedded memory region of a substrate and forming a plurality of transistor devices within a logic region of the substrate. A first isolation structure is formed within a boundary region of the substrate disposed between the logic region and the embedded memory region. The first isolation structure is formed within a recess in the substrate. A logic wall is formed over the first isolation structure. The logic wall surrounds the embedded memory region and has a first height that is greater than heights of the plurality of memory devices. |
| priorityDate |
2017-07-26^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |