| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11573 |
| filingDate |
2020-07-29^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-06-07^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a273858ccb8fdb5e612c294265b48096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_11db5d8800c485ccb18b6a442b8f7dd6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_295ef2eb792392e0ebcf26cc9c0afa42 |
| publicationDate |
2022-06-07^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11355194-B2 |
| titleOfInvention |
Non-volatile memory device |
| abstract |
A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line. |
| priorityDate |
2019-06-05^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |