| abstract |
Disclosed herein is an apparatus that includes a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits assigned to an associated one of the pad electrodes, a second semiconductor chip having a plurality of TSVs each electrically connected to an associated one of the pad electrodes and a plurality of second latch circuits assigned to an associated one of the TSVs, and a training circuit configured to perform a training operation on a signal path including the selected one of the pad electrodes and the selected one of the TSVs. The training circuit is configured to activate a fail signal when the signal path is determined to be defective. The fail signal is stored in the selected one of the first latch circuits and the selected one of the second latch circuits. |