| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c63bc5ef3ae590b0603de4587961cac3 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-54
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0679
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06N3-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-061
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0635 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06 |
| filingDate |
2021-01-13^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-07-12^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c3ab6dacbd4f88520bf05f08647e8d09
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f960d8ffe1356027264cd31cf85fe04 |
| publicationDate |
2022-07-12^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11385837-B2 |
| titleOfInvention |
Memory system |
| abstract |
A memory system includes a plurality of memory dies respectively having at least one channel, a controller configured to control the plurality of memory dies, and a base die configured for interfacing signal and data transmissions between the plurality of memory dies and the controller. The controller is configured to remap a logical channel address of the most frequently used channel to a physical channel address of a channel having a lowest temperature value to transmit the remapped physical channel address to the base die. |
| priorityDate |
2020-01-07^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |