| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b6caea61bfde8a45e01a8deabff80d97 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11556
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11524
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11524
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11556
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1157 |
| filingDate |
2020-09-24^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2023-01-10^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_acee2aedae65067a83d2fc1bac774d00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_574de233d33e6c0acdbfac4b2811baa1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b126e7600dd83ec6d1e0b7de014cb86c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b11f3e7bd60c87e29aac63bde05c090e |
| publicationDate |
2023-01-10^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11552094-B2 |
| titleOfInvention |
Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same |
| abstract |
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion. |
| priorityDate |
2017-07-18^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |