| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-4402
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-1208
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-789 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50012 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0328
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-16 |
| filingDate |
2002-06-18^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ebfd66de412b433003eb43cc07555026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d4f3e7fc6819a6ac10ed54dbb1407d5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9016554e8a2c49006d1c082e0d9b3727
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fe9028674fea0cab65d921a64bedb529 |
| publicationDate |
2003-01-23^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2003016570-A1 |
| titleOfInvention |
Semiconductor integrated circuit |
| abstract |
A semiconductor integrated circuit having therein a plurality of memories, realizing an improved yield by efficiently repairing a defective bit in a memory. This semiconductor integrated circuit has: a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code or not and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the setting information from the setting circuit, converting the setting information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the setting information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide with each other. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012020175-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9252062-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6586823-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8325546-B2 |
| priorityDate |
2000-07-11^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |