| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4027 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0175
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40 |
| filingDate |
2002-12-04^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_94cf4de035d3df9edeb2c7a5b7f3732d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dfa915235920b2813a44615d3a1301b2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6658bc3894c03992596a0a605dda1310
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ecdaf520ed99224377b8af005ed97b11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b1823ea73f73d9f38a3c78447af32747 |
| publicationDate |
2003-09-11^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2003169073-A1 |
| titleOfInvention |
Logic circuitry-implemented bus buffer |
| abstract |
A bus buffer has a controller to generate several control signals; a first terminal via which a first-directional signal is input whereas a second-directional signal is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first internal circuit and a first output buffer; a second-directional signal processor, provided between the second and first terminals, having a second internal circuit and a second output buffer; a first input buffer having a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals; and a second input buffer having a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal, for holding the input to the input buffers at a certain level to decrease a current to pass these circuits, thus achieving low power consumption. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007101026-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10891396-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7668977-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017344759-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009070505-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105960669-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015220462-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9898428-B2 |
| priorityDate |
2002-03-06^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |