| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_29c8490843b2973c9981b37d1f1f885c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_aa9588f1d3d2b19d1757e13e31e115ea |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78687
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1054
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate |
2005-03-22^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5111132a003a001ee0c326cacc6c70a3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a28600f577a20c8c905527694bca1f32 |
| publicationDate |
2005-10-06^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2005218438-A1 |
| titleOfInvention |
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
| abstract |
A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8921909-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9825150-B2 |
| priorityDate |
2004-03-31^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |