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filingDate 2006-08-11^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bd6bb4783b3cf913d33ee5de6a56c091
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publicationDate 2007-03-01^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2007047371-A1
titleOfInvention Semiconductor transistor with multi-level transistor structure and method of fabricating the same
abstract Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell transistor layers stacked in the cell array region, and a plurality of peripheral circuit transistors formed in the peripheral region. The cell transistor layers may be formed in the cell array region at a lower level than the peripheral region.
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