| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6cbec14264d3734f2980951ab8af96b8 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02B30-70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-095
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/F25B2600-021
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-123
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02P2201-03 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02P29-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02K19-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02P27-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K7-20936
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/F28D15-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K7-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/F25B49-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-12 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02P27-04 |
| filingDate |
2007-10-31^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1364d4eca4d19ba30a8f83a2334ade60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_db0419abca6f75d55abb8ad096142de0 |
| publicationDate |
2008-07-24^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2008174258-A1 |
| titleOfInvention |
System and method to extend synchronous operation of an active converter in a variable speed drive |
| abstract |
Systems and methods for synchronous operation of variable speed drives having active converters include extending the synchronous operation of an active converter to the AC mains voltage during complete line dropout. A phase angle control circuit includes a squaring amplifier, a first phase-lock loop circuit associated and a second phase-lock loop circuit. The squaring amplifier receives the AC power source and outputs a rectangular output signal to a pair of phase lock loop (PLL) circuits. The first PLL circuit with a first lag-lead filter is configured with a high cutoff frequency to provide the converter stage with a phase angle parameter; and the second phase-lock loop circuit including a second lag-lead filter configured to have a low cutoff frequency to provide the lag-lead filter the capability of storing the phase angle of the mains voltage during mains interruption. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10083788-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013524753-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111490538-A |
| priorityDate |
2007-01-22^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |