http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009150619-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b7317808024e524eea40a6c5a5ad6a22 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0826 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-46 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-0817 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-0831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08 |
| filingDate | 2005-11-08^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ec64d5c64346c4a6cd7d3e2968bbfc93 |
| publicationDate | 2009-06-11^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2009150619-A1 |
| titleOfInvention | Coherent caching of local memory data |
| abstract | A multi processor system 1 comprises a plurality of processors 21 to 25 , a system bus 30 and a main system memory 40 . Each processor 21 to 25 is connected to a respective cache memory 41 to 45 , with each cache memory 41 to 45 in turn being connected to the system bus 30 . The cache memories 41 to 45 store copies of data or instructions that are used frequently by the respective processors 21 to 25 , thereby eliminating the need for the processors 21 to 25 to access the main system memory 40 during each read or write operation. Processor 25 is connected to a local memory 50 having a plurality of data blocks (not shown). According to the invention, the local memory 50 has a first port 51 for connection to its respective processor 25 . In addition, the local memory 50 has a second port 52 connected to the system bus 30 , thereby allowing one or more of the other processors 21 to 24 to access the local memory 50 . The invention enables the coherent caching of local memory data, using local memory devices that are less expensive, faster, and having more predicable timing than cache memories. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105095145-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8291175-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011093646-A1 |
| priorityDate | 2004-11-24^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID54740 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID129747297 |
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