| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_73a7ce7a4956376042c57acac1a79fb9 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-12 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7841
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-118 |
| filingDate |
2010-09-22^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_634d27e6f4a139bdfd24036fcb3dcb5d |
| publicationDate |
2011-01-13^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2011007541-A1 |
| titleOfInvention |
Floating body memory cell system and method of manufacture |
| abstract |
A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016369993-A1 |
| priorityDate |
2005-06-20^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |