| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_73a7ce7a4956376042c57acac1a79fb9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8ba193638e0206105df1c51b43dc4b58
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_717c2eb63e678ec884e169d6578d4e94 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-71
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-33 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0038
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0023 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-10 |
| filingDate |
2011-03-03^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd8714470117cd5edeeacde9cb7edb84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fb452b8157024ff6e8c57323768f4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fc6b1381f16c5f823681f7cbac4ed812 |
| publicationDate |
2012-09-06^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2012224409-A1 |
| titleOfInvention |
Three dimensional memory system with page of data across word lines |
| abstract |
A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. One page of data is stored across multiple word lines by programming non-volatile storage elements connected to one column of bit lines and multiple word lines while maintaining the selection of the one column of bit lines. In one embodiment, programming non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2021243641-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016071594-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012224410-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9053766-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016019963-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9202533-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9449694-B2 |
| priorityDate |
2011-03-03^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |