| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9ec030fc062b270c25327af9127bed3a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09781
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49894
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73204
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-0055
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T29-49128
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-15
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-145 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-486
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4644
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-0271
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-0298
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49827 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-02 |
| filingDate |
2013-03-15^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ae517c1cd95f62af62a872aafef71e57 |
| publicationDate |
2013-10-10^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2013264100-A1 |
| titleOfInvention |
Wiring Substrate and Method for Manufacturing Wiring Substrate |
| abstract |
A method for manufacturing a wiring substrate includes alternately stacking first wiring patterns and first insulative layers on a first surface of a core substrate and alternately stacking second wiring patterns and second insulative layers on a second surface of the core substrate at an opposite side of the first surface. The number of the second insulative layers excluding the outermost second insulative layer differs from the number of the first insulative layers. The method further includes forming a via hole in the outermost first insulative layer to expose a portion of the outermost first wiring pattern, and exposing the outermost second wiring pattern by reducing the outermost second insulative layer in thickness. The method further includes forming a via in the via hole and forming a wiring pattern, which is connected by the via to the outermost first wiring pattern, on the outermost first insulative layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9780043-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015179560-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9257386-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017170130-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021392758-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2015162607-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11430725-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10978383-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015282323-A1 |
| priorityDate |
2012-04-10^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |