http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014281240-A1

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publicationNumber US-2014281240-A1
titleOfInvention Instructions To Mark Beginning and End Of Non Transactional Code Region Requiring Write Back To Persistent Storage
abstract A processor in described having an interface to non volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non volatile random access memory as persistence storage.
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