http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016125956-A1

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filingDate 2014-10-30^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a3e91f5187065038be2e73e8d63871e0
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publicationDate 2016-05-05^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2016125956-A1
titleOfInvention Erase Stress and Delta Erase Loop Count Methods for Various Fail Modes in Non-Volatile Memory
abstract Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb.
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