| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9985d583b30ac1151ed99d3b3cbc1985 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-1776
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17728
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L47-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L47-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L47-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-177 |
| filingDate |
2016-08-02^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7c8f8eb95ea8b10aa04f38c83fe19866
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_03bc5d055ba0ccf70367ac0b9e64d94c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_573c6abe2b4e8eeca4e09aec75f16731
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e47a7d1b65470d849c23ae4dc67aae38 |
| publicationDate |
2018-02-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018041328-A1 |
| titleOfInvention |
Dynamic clock-data phase alignment in a source synchronous interface circuit |
| abstract |
The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10439615-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019149154-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10666261-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019140649-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11621713-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10218360-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11128301-B2 |
| priorityDate |
2016-08-02^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |