| abstract |
A Bitcoin mining hardware accelerator is described. A System on Chip implementing a Bitcoin mining hardware accelerator may include a processor core and a hardware accelerator coupled to the processor core, the hardware accelerator to mine digital currency. The hardware accelerator may include a first computational block, including a message digest datapath, wherein the first computational block is to: precompute a first summation of a 32-bit message (W i ), a 32-bit round constant (K i ), and a content of a first shifted state register (G i−1 ), and store a result of the first summation in a state register (H i ). The Bitcoin mining hardware accelerator may further include a second computational block comprising a message scheduler datapath. |