| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-441
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-467
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66969
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-441
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-467
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2017-09-19^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_18d3774b9418001a0362712c9b546091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f4224b38a2db39a0cc50356a77f0bbd5 |
| publicationDate |
2018-04-12^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018102434-A1 |
| titleOfInvention |
Vertical channel oxide semiconductor field effect transistor and method for fabricating the same |
| abstract |
A semiconductor device includes: a channel layer surrounded by a source layer; a first dielectric layer around the source layer; a gate layer around the channel layer and on the source layer; a first oxide semiconductor layer between the gate layer and the channel layer; a second oxide semiconductor layer between the gate layer and the drain layer; a second gate dielectric layer between the second oxide semiconductor layer and the drain layer; a drain layer on the gate layer and around the channel layer; and a second dielectric layer around the drain layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3857604-A4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023173914-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019172909-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11658246-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10825898-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10559661-B2 |
| priorityDate |
2016-10-11^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |