http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018342626-A1

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filingDate 2018-07-16^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1eb8ae02be349996a4e53a3233c4c091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b00d2cbe5ecbfc704bced39e838c2e3
publicationDate 2018-11-29^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2018342626-A1
titleOfInvention Trench Vertical JFET With Ladder Termination
abstract A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.
priorityDate 2015-07-14^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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