| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_99505f5f312672820e9f78c254c00a4d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2209-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-588
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-576
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-72
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-73
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L9-3278
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-86 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-73
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-58
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L9-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-72 |
| filingDate |
2018-06-20^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6cb9403e70c477e1daf338325d960f9f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a69deea738abaa39040fc78156d19ac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_632804a160e64ff3fa3e352a20d48c86 |
| publicationDate |
2018-12-27^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018375670-A1 |
| titleOfInvention |
Method for securing an integrated circuit during fabrication |
| abstract |
The invention relates to a method of securing an integrated circuit during its fabrication on a wafer, said method including the following steps:n delimitation of said wafer of the integrated circuit ( 1 ) into a first zone called a standard zone ( 5 a ) and a second zone called a security zone ( 5 b ), and creation of a random connection tracks network ( 7 b ) in said security zone ( 5 b ) configured to interconnect a set of conducting nodes ( 9 b ) thus forming a physical unclonable function modelled by random electrical continuity that can be queried through said set of conducting nodes using a challenge-response authentication protocol. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11791290-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11444041-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3889683-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11176300-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11489012-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11631646-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11276652-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/FR-3108780-A1 |
| priorityDate |
2017-06-21^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |