| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bf83328d853bc7476ca10212837b3a01 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0408
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0425
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11524 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11524
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| filingDate |
2018-09-11^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_66c1e6e4b43f591948a4f5dde55f1e0b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d94d2ca06c8000dd0290e724abfcf81
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f0022574bc60cbfa4e01da131ca1e7f |
| publicationDate |
2020-03-12^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020083237-A1 |
| titleOfInvention |
Transistor device, memory arrays, and methods of forming the same |
| abstract |
In a non-limiting embodiment, a memory array is provided having a transistor device. The transistor device includes transistor device first, second and third doped regions in a substrate. The transistor device further includes a first transistor device select gate over a region between the transistor device first doped region and the transistor device second doped region, and a second transistor device select gate over a region between the transistor device first doped region and the transistor device third doped region. The transistor device further includes a transistor device dielectric barrier extending between the first transistor device select gate and the second transistor device select gate. A width of the dielectric barrier compared to a width of the first transistor device select gate and/or the second transistor device select gate may have a ratio ranging from 0.33:1 to 5:1. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11164881-B2 |
| priorityDate |
2018-09-11^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |