| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6a5092c4fee1e0747e3812acbefbb548
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b5e51fd2c13a2872d35c44c68a5f7103
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9605d542534be164019aff38b5020229
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1f51034908ee38e4b296286533d0f16e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10844
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate |
2019-12-23^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b01e50f6546edc5348f48e9ca8ec4676
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2115f2b581ce569fcac5e1773df3da06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2295be61c38ecfc1f038cbee72c4dbd1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4eebebed5d8f32a622174d3f10625fe3 |
| publicationDate |
2020-07-02^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020212051-A1 |
| titleOfInvention |
Memory device having shared access line for 2-transistor vertical memory cell |
| abstract |
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region. |
| priorityDate |
2018-12-26^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |