| abstract |
A high-voltage semiconductor device is provided. The device includes a semiconductor substrate, a gate dielectric layer, a T-shaped gate, a dielectric neck support, an etch stop feature, a pair of drift regions, and a pair of source/drain regions. The semiconductor substrate has a high-voltage well region. The gate dielectric layer is on the semiconductor substrate. The T-shaped gate is on the gate dielectric layer. The T-shaped gate includes overhangs that extend beyond the neck portion of the T-shaped gate. The dielectric neck support is disposed underneath the overhangs of the T-shaped gate. The etch stop feature is disposed underneath the dielectric neck support. The drift regions are disposed on opposite sides of the T-shaped gate in the high-voltage well region. The source/drain regions are disposed in the pair of drift regions. |